1. Field of the Invention
The present invention relates to a wire bonding method and a semiconductor package manufactured using the method, and, more particularly, the present invention relates to a wire bonding method and semiconductor package including a plurality of electrically interconnected semiconductor chips.
2. Description of the Related Art
Conventionally, a semiconductor package may include a plurality of semiconductor chips that are stacked or arranged side by side on a printed circuit board, a lead frame or a circuit film. (The descriptions below will be given mainly with reference to a printed circuit board.) Such semiconductor packages are known as stack-type semiconductor packages or multi-chip module (MCM) packages, respectively.
Often in such packages, one or more of the semiconductor chips are electrically connected to metal circuit patterns of the printed circuit board through conductive wires, which are sometimes called bond wires. The semiconductor chips are also electrically connected to one another through conductive wires bonded between their respective input and output pads.
A stack-type semiconductor package 100xe2x80x2 is illustrated in FIG. 1a, and a state of the stack type semiconductor package before encapsulation is illustrated in FIG. 1b. 
As shown in FIGS. 1a and 1b, a first semiconductor chip 2 is provided. A plurality of rows (for example, two staggered rows) of first input and output pads 2a are formed on an upper surface of the first semiconductor chip 2. A second semiconductor chip 4 is stacked on and affixed to the upper surface of the first semiconductor chip 2 by an adhesive means 6. Semiconductor chip 4 is located within input and output pads 2a of semiconductor chip 2. One row of second input and output pads 4a is formed on an upper surface of the second semiconductor chip 4.
A printed circuit board 20 is affixed to a lower surface of the first semiconductor chip 2 by another adhesive means 6.
As well known in the art, the printed circuit board 20 includes a resin layer 22. Electrically conductive circuit patterns are formed on the upper and lower surfaces of the resin layer 22. In particular, first circuit patterns 24, which include bond fingers 24a, are formed on the upper surface of the resin layer 22 outside the perimeter of first semiconductor chip 2. Second circuit patterns 24, which include ball lands 24b, are formed on the lower surface of the resin layer 22. The first and second circuit patterns 24 are electrically connected with each other through via-holes 25 through resin layer 22. On the upper surface of the resin layer 22, the first circuit patterns 24, excluding the bond fingers 24a, are coated with cover coats 26 or the like. Likewise, on the lower surface of the resin layer 22, the second circuit patterns 24, excluding the ball lands 24b, are coated with cover coat 26 or the like.
Some of the first input and output pads 2a of the first semiconductor chip 2 are electrically connected to second input and output pads 4a of the second semiconductor chip 4 through first conductive wires 8a that extend between them. Other first input and output pads 2a of the first semiconductor chip 2 are electrically connected to the bond fingers 24a of the printed circuit board 20 through second conductive wires 8b. Particular wires 8a, 8b may carry a ground voltage, power supply voltage, or data/instruction signals.
A hardened encapsulating section 30 of a predetermined shape covers the first semiconductor chip 2, the second semiconductor chip 4, the first and second conductive wires 8a and 8b, and the inner portion of the upper surface of circuit board 20, thereby protecting those components from the external environment.
Conductive balls 40 are fused to the ball lands 24b on the lower surface of the printed circuit board 20, and function as input and output terminals for communication with semiconductor chips 2, 4.
Hereinafter, a method for electrically connecting the first and second semiconductor chips 2 and 4 with each other through the conductive wires 8a and for electrically connecting first semiconductor chip 2 and the bond fingers 24a of the printed circuit board 20 through conductive wires 8b will be described with reference to FIGS. 2a through 2d. 
First, conductive balls 8d each having a predetermined size are formed with a wire bonder on some of the first input and output pads 2a of first semiconductor chip. 2. After the balls 8d are formed, the conductive wires drawn from balls 8d are cut off (see FIG. 2a). The drawing reference numeral 50 represents a capillary portion of a wire bonder for implementing a wire boding operation.
Then, to electrically connect the two semiconductor chips 2 and 4, one end of each of a plurality of conductive wires 8a are bonded to selected ones of the second input and output pads 4a of the second semiconductor chip 4, and the opposite end of those conductive wires 8a are each connected to one of the conductive balls 8d that were previously formed on some of the first input and output pads 2a of the first semiconductor chip 2 (see FIGS. 2b and 2c). To accomplish this wire bond between semiconductor chips 2 and 4, balls are formed by capillary 50 using the conductive wire material, and the balls are fused to the selected second input and output pads 4a of the second semiconductor chip 4. Capillary 50 then forcibly squeezes and fuses the opposite portion of each conductive wire against a ball 8d. Next, capillary 50 cuts the conductive wire.
Subsequently, wire bonds 8b are connected between other first input and output pads 2a of the first semiconductor chip 2 and bond fingers 24a of printed circuit board 20.
However, this conventional wire bonding method, and the resulting semiconductor packages, suffer from defects due to the fact that conductive balls 8d are formed in advance on some of the input and output pads of the first semiconductor chip 2, afterwhich an end of a wire 8a is bonded to each of the balls 8d. This can lead to an inferior wire bond connection, and reduced bonding yield.
Moreover, since the wire bonding operation is implemented in a manner that brings capillary 50 into contact with the conductive balls 8d, the lifetime of capillary 50 can be shortened, and the tip of capillary 50 can be seriously contaminated with the material of balls 8d. 
Furthermore, because a separate process for forming the conductive balls 8d is required, wire bonding time is lengthened and the manufacturing cost of the entire semiconductor package is increased.
On the other hand, if the first and second semiconductor chips were directly wire bonded with each other without conductive balls 8d, the input and output pads of the first semiconductor chip 2 can be broken by vibration energy of capillary 50, or first semiconductor chip 2 itself can be cracked by capillary 50. In view of this grave possible outcome, the wire bonding method using conductive balls 8d has been adopted.
One object of the present invention is to provide a wire bonding method for a semiconductor package containing a plurality of semiconductor chips. The semiconductor chips may be stacked one on top the other or arranged side by side on the same horizontal plane. The plural semiconductor chips are electrically interconnected using the disclosed methods without suffering from the problems associated with the conventional wire bonding methods described above.
Another object of the present invention is to provide a wire bonding method which can lengthen the lifetime of a capillary of a wire bonder and reduce manufacturing costs.
Another object of the present invention is to provide a reliable semiconductor package that includes a plurality of electrically interconnected semiconductor chips (either stacked or side by side) and can be manufactured effectively and efficiently.
In order to achieve the above objects and others, an exemplary embodiment of the present invention includes a wire bonding method comprising the steps of: providing a planar circuit board having a resin layer and possessing a chip mounting region at a center portion of the resin layer, the circuit board being formed with a plurality of circuit patterns outside the chip mounting region and one or more transfer patterns between the chip mounting region and the circuit patterns; affixing plural semiconductor chips to the circuit board in the chip mounting region, either in a stack or arranged side by side in the same horizontal plane; electrically connecting input and output pads of one semiconductor chip among the semiconductor chips to one or more of the transfer patterns of the circuit board through conductive wires bonded between them; and electrically connecting input and output pads of another semiconductor chip to the same respective transfer patterns of the circuit board through conductive wires bonded between them, thereby electrically connecting the semiconductor chips with one another through one or more pairs of bond wires and a transfer pattern bonded between the bond wires of each pair.
The circuit board so provided can be implemented such that at least one transfer pattern is formed between the chip mounting region and the circuit patterns radiating from the chip mounting region.
The transfer patterns can be short, planar, rectangular, electrically-isolated pads having a lengthwise orientation that is perpendicular to, or substantially perpendicular to, a lengthwise direction of the adjacent circuit patterns. The transfer patterns may be formed of copper, Alloy 42 or some other metal, and may be plated with silver (Ag) or gold (Au).
Alternatively, a predetermined number of circuit patterns among the plurality of circuit patterns can be used as the transfer patterns.
An exemplary embodiment of a semiconductor package within the present invention comprises: at least one first semiconductor chip having input and output pads; at least one second semiconductor chip having input and output pads, the second semiconductor chip being stacked on or positioned laterally adjacent to the first semiconductor chip; a circuit board affixed by an adhesive means to a lower surface of the first semiconductor chip or to lower surfaces of adjacent first and second semiconductor chips, the circuit board having a resin layer and including a plurality of electrically-conductive circuit patterns and one or more transfer patterns, the circuit board possessing ball lands formed on an upper surface or a lower surface of the resin layer in such a way as to be connected with the circuit patterns; a plurality of conductive wires, with each wire being electrically connected between one of the input and output pads of the first or second semiconductor chips and the transfer patterns, or between one of the input and output pads of the first and second semiconductor chips and the circuit patterns; a hardened encapsulating material that covers the first semiconductor chip, the second semiconductor chip, the conductive wires, and at least one surface of the circuit board, wherein said encapsulating material protects those components from the external environment; and conductive balls fused to the ball lands of the circuit board.
In such an embodiment, at least one transfer pattern can be formed between the first and second semiconductor chips and/or adjacent circuit patterns. Moreover, the transfer pattern(s) can have a lengthwise direction that is perpendicular to, or substantially perpendicular to, a lengthwise direction of the circuit patterns. The transfer patterns can be metal (e.g., Cu) plated with silver (Ag) or gold (Au).
Alternatively, the transfer patterns can comprise a predetermined number of circuit patterns among the plurality of circuit patterns.
The exemplary wire bonding method and semiconductor package enjoy numerous advantages compared to the conventional method and package described above. For example, by virtue of the transfer patterns, the input and output pads of the first and second semiconductor chips may be electrically connected with one another with an increased bonding yield. In addition, since the tip of the capillary of the wire bonder is not pressed onto a pre-formed ball 8d, contamination of the capillary with foreign material is avoided and the lifetime of the capillary can be lengthened. Furthermore, because it is not necessary to pre-form balls on the input and output pads of the first semiconductor chip, the manufacturing procedure is simplified and manufacturing costs are reduced.